Method and device for frequency synthesis using a phase locked loop

ABSTRACT

The present invention relates to a frequency synthesis system and device using a phase locked loop.  
     A frequency synthesis method using a phase locked loop including a phase comparator, said method including a step of switching from a fractional frequency division operating mode to an integer frequency division operating mode after a time or time-delay for stabilizing operation of said loop has elapsed, which method is characterized in that it consists of effecting said operating mode switching by masking or eliminating a portion of the pulses of a reference signal (Sref) and a comparison signal (Scomp) before they are applied to inputs of the phase comparator ( 3 ).

[0001] The present invention relates to frequency synthesis, inparticular for the modulating and demodulating signals, and provides afrequency synthesis method and system using a phase locked loop andhaving a short phase locking time.

[0002] Many methods and systems for synthesizing frequencies to providean output signal whose frequency is an integer multiple of the frequencyof a reference signal are known in the art, in particular methods andsystems using a phase locked loop. In these methods and systems, theoutput signal is compared to a reference signal, normally afterfrequency division, and the phase difference controls the output.

[0003] The output signal is generally generated by a voltage-controlledoscillator (VCO) to which the filtered output signal of the phasecomparator is applied, constituting a frequency control input signal.

[0004] For example, these methods and systems find applications in thesend and receive modules of communication systems, in particular ofradiocommunication systems, constituting means for changing send orreceive channels.

[0005] Frequency synthesizers have been developed more recently thatintegrate fractional frequency dividers in their phase locked loop andcan supply an output signal with virtually any frequency.

[0006] On changing channel, it is necessary to modify the frequency ofthe output signal and therefore to lock the phase locked loop to saidnew frequency.

[0007] These frequency changing and locking procedures lead tonon-negligible waiting times and unnecessary consumption of energy andare not user friendly.

[0008] To shorten these procedures, it has been proposed in particularto use a fractional division phase locked loop with a variable cut-offfrequency band and to precharge an upstream capacitor.

[0009] However, this solution is difficult and delicate to implement,necessitates supplemental outputs and an additional implementationsurface area, and increases energy consumption.

[0010] An object of the present invention is to alleviate the drawbackspreviously cited and to propose a solution which can greatly improve thelocking time using a fractional phase locked loop without generatingunwanted radio frequency interference.

[0011] To this end, the present invention provides a frequency synthesismethod using a phase locked loop including a phase comparator, saidmethod including a step of switching from a fractional frequencydivision operating mode to an integer frequency division operating modeafter a time or time-delay for stabilizing operation of said loop haselapsed, which method is characterized in that it consists of effectingsaid operating mode switching by masking or eliminating a portion of thepulses of a reference signal and a comparison signal before they areapplied to inputs of the phase comparator.

[0012] It also provides a frequency synthesizer system using a phaselocked loop and including a generator whose output signal has afrequency controlled as a function of the signal delivered by a phasecomparator whose inputs receive a reference signal and a comparisonsignal coming from a feedback subsystem connecting the output of saidcontrolled frequency generator to an input of said phase comparator andintegrating a fractional frequency divider, characterized in that italso includes a generator for generating masking or elimination signalsapplied, as command or authorization signals, to discriminator or filtercircuits connected in series, one in the transmission line for thereference signal and the other in the feedback subsystem immediatelyupstream of the corresponding inputs of the phase comparator, switchingfrom the fractional frequency division phase locked loop operating modeto the integer frequency division phase locked loop operating mode beingeffected by applying said masking or elimination signals.

[0013] The basic idea of the present invention lies in switching from afractional division phase locked loop (with no additionalimplementation) to a conventional phase locked loop (with integerdivision) after the stabilization time delay, with or withoutmodification of the bandwidth of said phase locked loop and, in anyevent, without generating interference.

[0014] The solution proposed by the invention leads to masking of somepulses, so that the phase comparator is activated as in a conventionalphase locked loop after a particular time-delay.

[0015] The invention will be better understood from the followingdescription, which relates to a preferred embodiment, provided by way ofnon-limiting example, and explained with reference to the accompanyingdiagrammatic drawings, in which:

[0016]FIG. 1 is a block diagram of a frequency synthesizer systemaccording to the invention,

[0017]FIG. 2 represents timing diagrams of reference, comparison andmasking signals before switching (fractional phase locked loop operationmode), and

[0018]FIG. 3 represents timing diagrams of reference, comparison andmasking signals after switching (conventional phase locked loopoperation mode).

[0019] The present invention relates to a frequency synthesis methodusing a phase locked loop 2 including a phase comparator 3, the methodincluding a step of switching from a fractional frequency divisionoperating mode to an integer frequency division operating mode after atime-delay for operation of said loop 2 to stabilize has elapsed.

[0020] According to the invention, said operating mode switching iseffected by periodically masking or eliminating a portion of the pulsesof the reference signal Sref and the comparison signal Scomp before theyare applied to the inputs of the phase comparator 3.

[0021] Said masking or said elimination preferably begins after apredetermined time delay (an optimum value for which can be determinedbeforehand, by trial and error), in a fraction of the time allocated forlocking the phase locked loop 2.

[0022] The invention therefore aims to exploit the much greater numberof pulses applied to the phase comparator 3 in the fractional divisionphase locked loop (PLL) operating mode in order to lock the loop faster,without having to accept the drawbacks associated with theimplementation and use of a fractional division loop.

[0023] As shown by comparing the FIGS. 2 and 3 timing diagrams, all ofthe pulses of the signals Scomp and Sref present in the conventional PLLoperating mode are already present in the signals in the fractionaldivision PLL operating mode, the change from the second mode to thefirst being effected by simply applying a mask to retain only thenecessary pulses in said second operating mode.

[0024] In a preferred embodiment of the invention, the masking orelimination is effected by generating a signal Smask for filtering ordiscriminating between the pulses of the reference signal Sref and thecomparison signal Scomp coming from the feedback subsystem 2′ of saidphase locked loop 2.

[0025] In a first embodiment, the masking or elimination signal Smask isa two-state signal and is applied, as a change command or changeauthorization signal, to circuits 4, 4′ forming transfer locks andconnected in series in the line for transmitting the reference signalSref and in the feedback subsystem 2′ immediately upstream of the inputsof the phase comparator 3.

[0026] In a second embodiment, the masking or elimination signal Smaskis a two-state signal and is applied, possibly after inversion, to oneinput of AND gates 4, 4′ connected in series, one in the line fortransmitting the reference signal Sref and the other in the feedbacksubsystem 2′, and whose outputs are connected to the inputs of the phasecomparator 3, the other inputs of said AND gates 4, 4′ respectivelyreceiving the reference signal Sref and the comparison signal Scompcoming from the feedback subsystem 2′.

[0027] As shown in FIG. 1 of the accompanying drawings, the presentinvention also provides a frequency synthesizer system 1 using a phaselocked loop 2 and including a generator 5 (for example a VCO) whoseoutput signal frequency is controlled as a function of the signaldelivered by a phase comparator 3 whose inputs receive a referencesignal Sref and a comparison signal Scomp coming from a feedbacksubsystem 2′ connecting the output of said controlled frequencygenerator 5 to an input of said phase comparator 3 and integrating afractional frequency divider 6.

[0028] This system 1 is characterized in that it also includes agenerator 7 for generating masking or elimination signals Smask appliedas command or authorization signals to discriminator or filter circuits4, 4′ connected in series, one in the line for transmitting thereference signal Sref and in the other in the feedback subsystem 2′immediately upstream of the corresponding inputs of the phase comparator3, the switching from a fractional frequency division phase locked loopoperating mode to an integer frequency division phase locked loopoperating mode being effected by applying said masking or eliminationsignals Smask.

[0029] In a preferred embodiment of the invention, the generator 7 forgenerating the masking or elimination signals Smask delivers a two-stateor squarewave signal, after a predetermined time-delay, in a fraction ofthe time allocated for locking the phase locked loop 2, said masking orelimination signal Smask having a variable cyclic ratio.

[0030] Consequently, the system 1 operates with a fractional divisionphase locked loop during a transient locking phase and with aconventional phase locked loop whose output signal Sout is locked to therequired frequency during the permanent operation phase.

[0031] To synchronize the operation of the various circuits constitutingthe system 1 during the stabilization, locking, switching and permanentoperation phases, the reference signal Sref is applied as a sequencingsignal to the generator 7 for generating the masking or eliminationsignals Smask and to the fractional frequency divider 6.

[0032] Also, a signal Ssettim indicating the time interval allocated tolocking the phase locked loop 2 is delivered to said generator 7 forgenerating masking or elimination signals Smask and to a [charge pump8/integrator filter 9] module between the output of the phase comparator3 and the input of the generator 5 for generating the output signal Soutof said system 1.

[0033] For example, the discriminator or filter circuits 4, 4′ canconsist of circuits forming transfer locks or of logic gates, forexample AND or OR gates.

[0034] The invention also relates to a mobile telecommunication terminalincluding a frequency synthesizer device 1 as described above andemploying the method previously cited.

[0035] Of course, the invention is not limited to the embodimentdescribed and shown in the accompanying drawings, which can be modifiedwithout departing from the scope of protection of the invention, inparticular from the point of view of the composition of the variouscomponents or by substituting technical equivalents.

1. A frequency synthesis method using a phase locked loop including aphase comparator, said method including a step of switching from afractional frequency division operating mode to an integer frequencydivision operating mode after a time or time-delay for stabilizingoperation of said loop has elapsed, which method is characterized inthat it consists of effecting said operating mode switching by maskingor eliminating a portion of the pulses of a reference signal (Sref) anda comparison signal (Scomp) before they are applied to inputs of thephase comparator (3).
 2. A method according to claim 1, characterized inthat said masking or said elimination begins after a predeterminedtime-delay, in a fraction of the time allocated for locking the phaselocked loop (2).
 3. A method according to either claim 1 or claim 2,characterized in that the masking or elimination is effected bygenerating a signal (Smask) for filtering or discriminating betweenpulses of the reference signal (Sref) and the comparison signal (Scomp)coming from the feedback subsystem (2′) of said phase locked loop (2).4. A method according to claim 3, characterized in that the masking orelimination signal (Smask) is a two-state signal and is applied,possibly after inversion, to an input of AND gates (4, 4′) connected inseries, one in the line for transmitting the reference signal (Sref) andthe other in the feedback subsystem (2′), and whose outputs areconnected to inputs of the phase comparator (3), the other inputs ofsaid AND gates (4, 4′) respectively receiving the reference signal(Sref) and the comparison signal (Scomp) coming from the feedbacksubsystem (2′).
 5. A frequency synthesizer system using a phase lockedloop and including a generator whose output signal has a frequencycontrolled as a function of the signal delivered by a phase comparatorwhose inputs receive a reference signal and a comparison signal comingfrom a feedback subsystem connecting the output of said controlledfrequency generator to an input of said phase comparator and integratinga fractional frequency divider, characterized in that it also includes agenerator (7) for generating masking or elimination signals (Smask)applied, as command or authorization signals, to discriminator or filtercircuits (4, 4′) connected in series, one in the transmission line forthe reference signal (Sref) and the other in the feedback subsystem (2′)immediately upstream of the corresponding inputs of the phase comparator(3), switching from the fractional frequency division phase locked loopoperating mode to the integer frequency division phase locked loopoperating mode being effected by applying said masking or eliminationsignals (Smask).
 6. A system according to claim 5, characterized in thatthe generator (7) for generating masking or elimination signals (Smask)delivers a two-stage or squarewave signal after a predeterminedtime-delay in a fraction of the time allocated for locking the phaselocked loop (2).
 7. A system according to either claim 5 or claim 6,characterized in that the reference signal (Sref) is applied, as asequencing signal, to the generator (7) for generating masking orelimination signals (Smask) and to the fractional frequency divider (6)and in that a signal (Ssettim) indicating the time interval allocated tolocking the phase locked loop (2) is delivered to said generator (7) forgenerating masking or elimination signals (Smask) and to a [charge pump(8)/integrator filter (9)] module between the output of the phasecomparator (3) and the input of the generator (5) of the output signal(Sout) of said device (1).
 8. A device according to any of claims 5 to7, characterized in that the discriminator or filter circuits (4, 4′)form transfer locks.
 9. A device according to any of claims 5 to 7,characterized in that the discriminator or filter circuits (4, 4′) arelogic gates.
 10. A system according to any of claims 6 to 9,characterized in that the masking or elimination signal (Smask) has avariable cyclic ratio.
 11. A mobile radiotelecommunication terminal,characterized in that it includes a frequency synthesizer system (1)according to any of claims 5 to 10.